1. Field of the Invention
The invention relates in general to a method of identifying logical information in a programming and erasing cell by one-side reading scheme, and more particularly to the method of identifying logical information in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme.
2. Description of the Related Art
Semiconductor device, having the advantages that the information stored therein is not lost even the power supply is removed, so labeled as “non-volatile memory” is current widespread use today. The non-volatile semiconductor memory, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrical erasable programmable read only memory (EEPROM) and flash EEPROM, are used in various application.
Semiconductor EEPROM device involves more complicate processing and testing procedures than other non-volatile semiconductor memory devices, but having the advantage of electrically storing and removing data. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device. Flash EEPROM, similar to EEPROM, can be programmed and erased electrically but with additional ability of erasing memory cell at once. However, the manufacturing process of flash EEPROM is complicated and the production cost thereof is very expansive.
Many researches have been proposed, focusing on constructing a better memory cell based on the EEPROM model; for example, nitride read only memory (NROM) having high-density has been configured by modifying the traditional form of EEPROM cell. If the NROM device is programming (storing data into the device), a charge is injected and trapped in the charge-trapping layer. One significant characteristic of NROM is that a NROM cell is capable of storing two bits data. Both ends of the charge-trapping layer cane be programmed and erased as two individual bits. However, the NROM device has the problems such as high power consumption due to hot electron programming and read disturbance, which are potential issues for scaling ability.
Recently, a novel flash memory cell, similar to the structure of the NROM cell but meet the requirements of mass storage application, named “PHINES” (programming by hot hole injection nitride electron storage) is proposed. PHINES uses a nitride trapping storage cell structure, FN erase to raise the threshold voltage (Vt) and lower local Vt by hot hole injection.
FIG. 1 illustrates a sectional view of a two-bit PHINES cell. The PHINES cell comprises a substrate 12 (typically a P-type substrate), a source 14 and a drain 16 separated by the channel, and two buried PN junctions. The left PN junction is between the source 14 and the substrate 12, and the right PN junction is between the drain 16 and the substrate 12. Above the channel is an oxide-nitride-oxide (ONO) stack 17, comprising a silicon dioxide layer 18, a silicon nitrite layer 19 and a silicon dioxide layer 20. Also, a control gate 22 is formed over the ONO stack 17. The silicon dioxide layer 18 forms as an electrical isolation layer over the channel. The silicon nitrite layer 19 functions as a trapping storage layer. The silicon dioxide layer 20 electrically isolates the silicon nitride layer 19 and the control gate 22. The PHINES cell is capable of storing two bits of data. The dashed circles 24 and 26 represent a left-bit (L-bit) and a right-bit (R-bit), respectively. In the PHINES cell, the silicon nitrite layer 19 serves as the memory retention layer.
FIG. 2A schematically shows the L-Bit and the R-Bit at erased state. FIG. 2B schematically shows the L-Bit at programmed state and the R-Bit at erased state. As shown in FIG. 2A, before programming the PHINES cell, the L-Bit and the R-Bit need to be erased by FN electron injection so as to achieving high Vt state. The program is done by lowering local Vt through edge band-to-band hot hole injection. As shown in FIG. 2B, the L-Bit is programmed by hot hole injection while the R-Bit is still in erased state, thus local Vt of L-Bit is lower than that of R-Bit.
FIG. 3A˜FIG. 3H schematically show the state of erasing, programming and reading the PHINES cell and the related logical information of two bits. In FIG. 3A and FIG. 3E, the L-Bit and the R-Bit are at erased state. In FIG. 3B and FIG. 3F, the L-Bit is at programmed state and the R-Bit is at erased state. In FIG. 3C and FIG. 3G, the L-Bit is at erased state and the R-Bit is at programmed state. In FIG. 3D and FIG. 3H, the L-Bit and the R-Bit are at programmed state.
After applying a selected potential to the control gate, the L-Bit and the R-Bit are in erased state by electron injection, and the electrons are trapped in the silicon nitride layer 19, as shown in FIG. 3A. To read the R-Bit of the PHINES cell in the reverse direction, a selected read voltage (Vread) and a gate voltage (Vg) are applied to the source 14 and the control gate 22, respectively. Since the electrons are trapped in the silicon nitride layer 19, the logical information of the R-Bit of FIG. 3A is “0”.
In FIG. 3A˜FIG. 3D, the Vread is applied to the source 14 for reading the logical information of the R-Bit in the reverse direction. In FIG. 3E˜3H, the Vread is applied to the drain 16 for reading the logical information of the L-Bit in the reverse direction. Noted that a much wider depletion region must be sustained in the case of reading in the reverse direction. Thus, Vread should be large enough to create an adequate depletion region (regions 32 in FIG. 3A˜FIG. 3D, regions 34 in FIG. 3E˜3H), thereby shielding the state of the bit close to the electrode (source 14 in FIG. 3A˜FIG. 3D, drain 16 in FIG. 3E˜3H) for being applied by Vread.
In the case of reading in the reverse direction, the logical information of the R-Bit is determined according to the electrons trapping condition occurring in the R-Bit, whether in the L-Bit or not. Thus, the logical information of the R-Bit is “0” for the states of FIG. 3A and FIG. 3B; the logical information of the R-Bit is “1” for the state of FIG. 3C and FIG. 3D. Similarly, the logical information of the L-Bit is “0” for the state of FIG. 3E and FIG. 3G, the logical information of the L-Bit is “1” for the state of FIG. 3F and FIG. 3H. Accordingly, the logical information combination of a two-bit PHINES cell is “0 and 0”, “0 and 1”, “1 and 0” and “1 and 1”.
However, reading the PHINES cell in the reverse direction has the drawbacks, such as 2nd-bit effect (higher Vread applied for reading in the reverse direction) thereby limiting the sensing window and the scaling ability, and hole-enhance local-DIBL (drain induced barrier lowing) effect (FIG. 4).
FIG. 4 represents hole-enhance local-DIBL effect of the PHINES cell. It is assumed that only the L-Bit is programmed by hot hole injection while the R-Bit is unprogrammed. Curve (I) represents the relationship between Vt and programming time of L-Bit. Curve (II) represents the relationship between Vt and programming time of R-Bit. Although only the L-Bit is hot-hole programmed, the Vt of R-Bit is decreased from V1 (V1 in FIG. 4) to V12 when the Vt of L-Bit is decreased from V1 (V1 in FIG. 4) to V22. This situation is so-called as “hole-enhance local-DIBL effect”, and has the issue of controlling the operation window.